Semiconductor grain microstructures for photovoltaic cells

ABSTRACT

Photovoltaic structures for the conversion of solar irradiance into electrical free energy. In particular implementations, the novel photovoltaic structures can be fabricated using low cost and scalable processes, such as magnetron sputtering. In a particular implementation, a photovoltaic cell includes a photoactive conversion layer comprising one or more granular semiconductor and oxide layers with nanometer-size semiconductor grains surrounded by a matrix of oxide. The semiconductor and oxide layer can be a disposed between electrode layers. In some implementations, multiple semiconductor and oxide layers can be deposited. These so-called semiconductor and oxide layers absorb sun light and convert solar irradiance into electrical free energy.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application is a continuation of U.S. patent applicationSer. No. 11/923,070, filed Oct. 24, 2007, which claims the benefit ofthe following U.S. Provisional Applications:

1) Provisional Appl. Ser. No. 60/854,226, filed Oct. 24, 2006;

2) Provisional Appl. Ser. No. 60/857,967, filed Nov. 10, 2006; and

3) Provisional Appl. Ser. No. 60/859,593, filed Nov. 17, 2006.

TECHNICAL FIELD

The present disclosure generally relates to photovoltaics.

BACKGROUND

The maximum thermodynamic efficiency for the conversion ofnonconcentrated solar irradiance into electrical free energy for asingle-band semiconductor absorber is approximately 31% (W. Shockley, H.J. Queisser, J., Appl. Phys. 32, 510 (1961)]. This efficiency isattainable in semiconductors with band gap energies ranging from 1.25 to1.45 electronvolts (eV). For semiconductors, band gap generally refersto the energy difference between the top of the valence band and thebottom of the conduction band. The solar spectrum, however, containsphotons with energies ranging from about 0.5 to about 3.5 eV. Photonswith energies below the semiconductor band gap are not absorbed. On theother hand, photons with energies above the band gap create chargecarriers with a total excess kinetic energy, E_(k)(excess)=hv−E_(g),where hv is the photon energy. A significant factor limiting theconversion efficiency to 31% is that the excess kinetic energy (absorbedphoton energy above the semiconductor band gap) E_(k)(excess) is lost asheat through electron-phonon scattering. “Hot” electrons and holes thatare created by absorption of solar photons with energies larger than theband gap will relax to their respective band edges.

For a single-band-gap semiconductor absorber there are two ways toextract energy from hot carriers before they relax to the band edge. Onemethod produces an enhanced photovoltage, and the other method producesan enhanced photocurrent. The former method involves extraction of hotcarriers from a semiconductor absorber before they relax to theirrespective band edges. Extracting energy from hot carriers, before theyrelax to the band edge, is possible if the relaxation rate of hotcarriers to their respective band edges is slowed. In the latter method,hot carriers produce two or more electron-hole pairs—i.e., so-calledimpact ionization.

P-n junction solar cells are the most common solar cells, including alayer of n-type semiconductor in direct contact with a layer of p-typesemiconductor. If a p-type semiconductor is placed in intimate contactwith a n-type semiconductor, then a diffusion of electrons occurs fromthe region of high electron concentration (the n-type side of thejunction) into the region of low electron concentration (p-type side ofthe junction). The diffusion of carriers does not happen indefinitely,however, because of an opposing electric field created by this chargeimbalance. The electric field established across the p-n junctioninduces separation of carriers that are created as result of photonabsorption.

Dye-Sensitized solar cells and Quantum Dot-Sensitized solar cells aretwo next generation solar technologies. In dye-sensitized solar cells,dye molecules are chemisorbed onto the surface of 10 to 30 nanometer(nm) size titanium oxide (TiO₂) particles that have been sintered intohigh porous nanocrystalline 10 to 20 μm thick TiO₂ films. Upon the photoexcitation of dye molecules, electrons are injected from the excitedstate of dye into the conducting band of the TiO₂ creating a chargeseparation and producing photovoltaic effect. The original state of thedye is subsequently restored by electron donation from the electrolyte,usually an organic solvent containing redox system, such as theiodide/triiodide couple. It is generally accepted that, inDye-Sensitized solar cells, the electron transport through the oxide ispredominantly governed by diffusion, because the highly conductiveelectrolyte screens the interior of the cells from any applied electricfield.

In quantum dot-sensitized solar cells, semiconductor particles withsizes below 10 nm (so-called quantum dots) take the role of the dyemolecules as absorbers. In these solar cells the hot carriers mayproduce two or more electron-hole pairs, so-called impact ionization,increasing efficiency of these solar cells. Quantum dot-sensitized solarcells offer several other advantages. The band gaps and thereby theabsorption ranges are adjustable through semiconductor quantum dot sizeor composition. Furthermore, compared to organic dyes, quantum dotsensitization offers improved stability, since the surface of thesemiconductor quantum dot can be modified to improve its photostability.

A noted drawback of both Dye-Sensitized and Quantum Dot-Sensitized solarcells is long term stability due to the presence of electrolyte. Inorder to improve stability of quantum dot-sensitized solar cells, theredox electrolyte in these cells can be replaced with a solidhole-conducting material, such as spiro-OMeTAD, or a p-typesemiconductor. The former is called solid state Dye-Sensitized solarcell, if an absorber is a dye molecule, or solid state QuantumDot-Sensitized solar cells, if an absorber is a quantum dot. The lattersolar cell, including a p-type semiconductor, is called an extremelythin absorber (ETA) solar cell. In this solar cell, a porousnanocrystalline TiO₂ film is covered with a p-type semiconductorabsorber using an atomic layer deposition technique, or usingelectrochemical deposition. These techniques enable a conformaldeposition of a semiconductor on top of TiO₂. A p-type semiconductorfirst fills up the pores of porous TiO₂ film and then tops the wholestructure with a layer about 10 to 200 nm thick. Because of the roughTiO₂ surface and a conformal deposition of a p-type semiconductor, theinterface area between a p-type semiconductor and an oxide layerincreases more than 10 times in comparison to that for a flat TiO₂ filmcovered by a p-type semiconductor layer.

To decrease the relaxation rate of charge carriers, an absorbersemiconductor can be inserted between TiO₂ (n-type semiconductor) andthe solid hole conductor material. In this structure, the n-typesemiconductor (oxide, example: TiO₂) has a porous structure and theabsorber semiconductor is adsorbed at the surface of n-typesemiconductor forming individual quantum dots. The average size of theabsorber semiconductor quantum dots is below 10 nm to utilize theconfinement effect and reduce the relaxation rate of hot carriersincreasing efficiency of these solar cells. In the existing fabricationprocesses of solid state sensitized solar cells porous or rough TiO₂layer is filled (using-electrochemical deposition techniques) withabsorber semiconductor grains and covered with p-type semiconductor(using atomic layer deposition or electrochemical deposition techniques)or a different hole conducting inorganic material (using for examplespin coating of a solution of hole conductor and chlorobenzene (See J.Kruger, U. Bach, R. Plass, M. Piccerelli, L. Cevey, M. Graetzel, Mat.Res. Soc. Symp. Proc., 708, BB9.1.1 (2002)). The hole conductor may bean organic transport material. This organic charge transport materialmay be a polymer, like poly-tiophen or poly-arylamin. The hole conductormay be an organic hole conductor from the group consisting of spiro- andhetero spiro compounds of the general formula (1)

where φ is one of C, Si, Ge or Sn, and K1 and K2 are, independently oneof the other, conjugated systems. One example organic hole conductor isspiro-OMeTAD(2,2′,7,7′-tretakis(N,N-di-p-methoxyphenyl-amine)9-9′-spirobifluorene).The conductivity of pure spiro-OMeTAD is low. Therefore the materialcannot be used, without some modification, in solar cells. Rather,partial oxidation of spiro-OMeTAD by N(PhBr)₃SbCl₆ can be used tocontrol the dopant level and to increase the conductivity of the holeconducting layer. A second additive Li[CF₃SO₂]₂N can also be added,since Li+ ions have been shown to increase the current output andoverall efficiency of the device. The hole conductor matrix can beapplied by spin-coating of a solution of the hole conductor inchlorobenzene. MEH-PPV[poly[2-methoxy-[5-(2′-ethyl)hexyl]oxy-p-phenylenevinylene]] andPEDOT:PSS [poly(3,4-ethylenedioxythiophene)poly(styrenesulfonate)] canalso be used as hole conductor materials. To increase its conductivityPEDOT:PSS can be mixed with glycerin, N-methylpyrrolidone, andisopropanol.

SUMMARY

The present invention provides methods, apparatuses and systems directedto novel photovoltaic structures for the conversion of solar irradianceinto electrical free energy. In particular implementations, the novelphotovoltaic structures can be fabricated using low cost and scalableprocesses, such as magnetron sputtering. In a particular implementation,a photovoltaic cell includes a photoactive conversion layer comprisingone or more granular semiconductor and oxide layers with nanometer-sizesemiconductor grains surrounded by a matrix of oxide. The semiconductorand oxide layer can be a disposed between electrode layers. In someimplementations, multiple semiconductor and oxide layers can bedeposited. These so-called semiconductor and oxide layers absorb sunlight and convert solar irradiance into electrical free energy. Uponillumination with solar irradiance, the nanometer size semiconductorgrains, in some implementations, inject electrons or other chargecarriers (like holes) into the conducting band of oxide, creating chargeseparation and producing photovoltaic effect. Following chargeseparation, electrodes extract electrons and holes to produce current.

The properties of the semiconductor grains can be controlled, and insome instances varied, to achieve a variety of effects and advantages.For example, the size of the semiconductor grains can be configured tofacilitate extraction of charge carriers before they can relax to theband edge, increasing the efficiency of the photon conversion innanometer-sized semiconductor grains. In addition, the size and/orcomposition of the semiconductor grains in multiple semiconductor andoxide layers can be varied to match the band gaps of the semiconductorgrains to the solar energy spectrum. This can further reduce the energyloss due to the relaxation of charge carriers to their respective bandedges.

DESCRIPTION OF THE DRAWINGS

FIGS. 1 a to 1 g and 1 l illustrate example photovoltaic cell structuresaccording to various implementations of the invention.

FIGS. 1 h, 1 i and 1 j illustrate the microstructure configuration of asemiconductor and oxide layer according to an implementation of theinvention.

FIG. 1 k is a diagram illustrating how semiconductor grain diameter maybe determined according to one possible implementation of the invention.

FIGS. 2 a and 2 b provide example composite photoactive layers that maybe used in photovoltaic cells of the present invention.

FIGS. 3 a and 3 e provide example composite photoactive layers that maybe used in photovoltaic cells of the present invention.

FIGS. 4 a and 4 b provide example composite photoactive layers that maybe used in photovoltaic cells of the present invention.

FIGS. 5 a to 5 e provide example composite photoactive layers that maybe used in photovoltaic cells of the present invention.

FIG. 6 is a schematic diagram illustrating an example sputter depositionprocess.

FIG. 7 is a diagram illustrating the deposition of adatoms on asubstrate in a high-pressure, low mobility sputter deposition process.

FIGS. 8 a and 8 b provide example composite photoactive layers that maybe used in photovoltaic cells of the present invention.

FIGS. 9 a and 9 b provide example composite photoactive layers that maybe used in photovoltaic cells of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENT(S) A. Overview

FIGS. 1 a to 1 d illustrate example structures and configurations ofsolar cells according to several possible implementations of theinvention. As FIG. 1 a illustrates, a solar cell 100 may comprise, inoverlying sequence a glass or other transparent substrate 8000, atransparent conductive layer 7000, a photoactive conversion layer 80, asecond transparent conductive layer 7000 and a second glass or othertransparent material layer 8000. In a particular implementation, thetransparent conductive layer 7000 may be indium oxide doped with tinoxide.

In other implementations, solar cell 101, as FIG. 1 b shows, maycomprise (in overlying sequence) non-transparent substrate 8600, metalcontact layer 9000, photoactive conversion layer 80, transparentconductive layer 7000, and glass or other transparent material substrate8000. FIG. 1 c shows solar cell 102 comprising (in overlying sequence)glass substrate 8000, transparent conductive layer 7000, photoactiveconversion layer 80, metal contact layer 9000, and non-transparentprotective layer 8500.

As FIG. 1 d illustrates, photoactive conversion layer 80 may include aplurality of sub-layers including one or more of a seed layer 6000, oneor more interlayers 5000, one or more n-type semiconductor and oxidelayers 2101, and a hole conducting material layer 3000. FIGS. 1 e to 1 gshow other alternative photoactive conversion layers. For example, asFIG. 1 e illustrates, photoactive conversion layer 80 a may compriseseed layer 6000, interlayer 5000, p-type semiconductor and oxide layer2102, and electron conducting material layer 1000. The photoactiveconversion layer may include other layers as well. As FIGS. 1 f and 1 gshow, photoactive conversion layers 80 b, 80 c may include a metal andoxide layer 2200 disposed on the interlayer 5000.

Photoactive conversion layer 80 includes multiple sub-layers havingvarious conductive properties and other characteristics, which, incombination, can be configured to produce a photovoltaic effect inresponse to solar energy. The material composition, layer configurationand layer arrangement of the photovoltaic cells can be configured toachieve a variety of objectives. For example, the materials used inthese layers may be configured to create p-n heterojunctions. N-typesemiconductor and oxide layer 2101 and p-type semiconductor and oxidelayer 2102, in some implementations, are sensitizing or absorber layers.With reference to FIG. 1 d (for example), upon photo excitation,electrons are efficiently injected from the conducting band of thesemiconductor grains of n-type semiconductor and oxide layer 210 1 intothe conducting band of electron conducting material. creating a chargeseparation and producing photovoltaic effect. Regeneration of theabsorber semiconductor grains can occur by capture of electrons from thehole conducting material layer 3000.

One or more intrinsic semiconductor layers 21X0 (see, e.g. intrinsicsemiconductor layer 2110 in FIG. 2 a) can be disposed between thesep-type and n-type semiconductor layers, as well. The materialcomposition, layer configuration and layer arrangement of thephotovoltaic cells can be configured to achieve a variety of objectives.For example, depending on material choice. the nanometer-diameter grainsof the intrinsic semiconductor and oxide layer 21X0 can operate asabsorbers in a p-n heterojunction between an oxide material (such asTiO2) and a hole conducting material (such as OMeTAD). To achieveefficient electron injection into the electron conducting layer, thebottom edge of the conductive band of the absorber. E_(c)(absorber),should be higher than the bottom edge of the conductive band of theelectron conducting layer, E_(c)(electron conducting layer). On theother hand the top edge of the valence band of the absorber,E_(v)(absorber), should be lower than the top edge of the valence bandof the hole conducting layer, E_(v), or the Fermi level of organic holeconductor material, to promote efficient regeneration of the absorbersemiconductor grains. In other implementations, the layers of the cellstructure can be configured to create p-n junctions with an electricfield across the depletion region between a p-type semiconductor layerand an n-type semiconductor layer.

One or more intrinsic semiconductor layers can be disposed between thesep-type and n-type semiconductor layers, as well.

Glass layer 8000 can be a glass substrate or deposited layer made of avariety of materials, such as silicon dioxide. Alternatively, atransparent polymer can be used. Still further, one or more of thetransparent conducting layers 7000 can be replaced by metal contactsarranged in a grid (e.g., fingers and busbars) on one side (or bothsides) and a full area metal contact on the other side. Additionallayers, such as anti-reflection coatings can also be added. The layerstack can be deposited on glass, polymer or metal substrates. If thelayer stack is deposited on top of a non-transparent substrate, the topcontact is transparent to allow light penetration into the photoactiveconversion layer. Glass layer 8000 can be replaced by other suitableprotective layers or coatings, or be added during construction of asolar module or panel. Still further, the layers described herein may bedeposited on a flat substrate (such as a glass substrate intended forwindow installations), or directly on one or more surfaces of anon-imaging solar concentrator, such as a trough-like or Winston opticalconcentrator.

A.1. Semiconductor and Oxide Layer

Structurally, semiconductor and oxide layers 2101 and 2102 are granularlayers comprising a plurality of nanometer-diameter semiconductor grains98 contained in, or surrounded by, a matrix of oxide material 99. Inother words, the oxide material is dispersed at grain boundaries 97 ofthe semiconductor. For purposes of this disclosure, reference numbersfor the semiconductor and oxide layers follow a convention of 21Xy,where X denotes the sub-layer position and y denotes the type ofsemiconductor (y=1 corresponds to n-type, y=2 corresponds to p-type andy=0 corresponds to i-type or intrinsic semiconductor). Formation of thesemiconductor and oxide layers 21Xy is discussed below. In thesemiconductor and oxide layer(s), upon photoexcitation of semiconductorgrains 98, electrons are injected into the surrounding oxide matrix 99or generated charge carriers (electrons and holes) are separated by anelectric field created by p-type and n-type semiconductor materials inthe adjacent layers.

FIGS. 1 h to 1 i illustrate an example microstructure of thesemiconductor and oxide layer 21Xy according to one possibleimplementation of the invention. One skilled in the art will recognizethat these Figures are idealized representations of the microstructureof the semiconductor cylinder-like grains 98 and that the boundariesbetween the semiconductor grains and the oxide matrix may, and oftenwill, not be defined by perfect cylinders. For example, in thesemiconductor and oxide layers, the semiconductor grains will generallynot have a perfect cylindrical shape. In addition, in some instances,neighboring semiconductor grains may be in direct contact as opposed tobeing completely separated by oxide material. The size of cylinder-likesemiconductor grains in the semiconductor and oxide layer is defined bythe diameter and the height of these grains. The diameters of thesemiconductor grains at a given layer may vary from a minimum to amaximum grain diameter. The average semiconductor grain diameter can bedefined as the mean or average value of all semiconductor graindiameters in the semiconductor and oxide layer 21Xy. FIG. 1 k shows anexample of a semiconductor grain 98 surrounded by an oxide material.Since grains generally do not have a perfect cylindrical shape, thediameter of the grain can be defined as 2*(S/π)^(0.5) where S is thearea of the top surface of the grain, i.e., S is the surface area thatthe semiconductor grain shares with the layer deposited on top of thesemiconductor and oxide layer 21Xy. The average diameter of thesemiconductor grains in the semiconductor and oxide layer can varyconsiderably up to about 100 nm. However, a preferred average diameterof the semiconductor grains in the semiconductor and oxide layer can beup to 10, 15, 20 or 40 nm. The height of the semiconductor grain issubstantially equal to the thickness of the semiconductor and oxidelayer 21Xy. The thickness of the layers can vary considerably up toabout 4000 nm. However, a preferred thickness of the semiconductor andoxide layer can be up to 400 nm. In some implementations, multiplesemiconductor and oxide sub-layers (each with varying averagesemiconductor grain diameters ranging from 3 to 12 nm and thicknessesranging from 3 to 25 nm) can be deposited. In one example configuration,five semiconductor and oxide sub-layers with the average semiconductorgrain diameter, in descending order, of 12/10/7/5/3 nanometers andthicknesses, in descending order, of 25/10/7/5/3 nanometers can bedeposited. Still further, the oxide content of the semiconductor andoxide layers can range from 1 to 99 percent of a given layer by volume.However, a preferred oxide content of the semiconductor and oxide layerscan range from 5 to 75 percent of a given layer by volume.

As discussed above, multiple semiconductor and oxide layers may bedeposited. Furthermore, the semiconductor material in semiconductor andoxide layers may be an intrinsic semiconductor material, a p-typesemiconductor material, or an n-type semiconductor material. Variousimplementations discussed below utilize one or more of thesesemiconductor and oxide layers in varying configurations, combinationsand arrangements to yield high efficiency solar cells. As discussedabove, this disclosure refers to an intrinsic semiconductor and oxidelayers using a reference number convention of 21X0, where X equals alayer number from 1 to N (where N equals the number of layers).Similarly, this disclosure refers to n-type semiconductor and oxidelayers using a reference number convention of 21X1, where X equals alayer number from 1 to N. Lastly, this disclosure refers to p-typesemiconductor and oxide layers using a reference number convention of21X2, where X equals a layer number from 1 to N.

In the photovoltaic cells illustrated in FIGS. 2 a and 2 b, for example,intrinsic semiconductor grains in the semiconductor and oxide layer 2110operate as absorbers. In other words, light excites electrons in theabsorber semiconductor grains 98, which are injected into the conductionband of the oxide matrix 99 or into the conduction band of an electronconductor. The absorber semiconductor grains 98 are regenerated bycapture of electrons from the valence band of a hole conducting materiallayer (such as a p-type semiconductor). For intrinsic semiconductor andoxide layer 21X0, the semiconductor material may be an intrinsicsemiconductor comprising one or more of silicon (Si), germanium (Ge),tin (Sn), beta iron silicide (β-FeSi₂), indium antimony (InSb), indiumarsenic (InAs), indium phosphate (InP), gallium phosphate (GaP), galliumarsenic (GaAs), gallium antimony (GaSb), aluminum antimony (AlSb),silicon carbide (SiC), tellurium (Te), zinc antimony (ZnSb), mercurytelluride (HgTe), led sulfide (PbS), led selenide (PbSe), led telluride(PbTe), cadmium sulfide (CdS), cadmium selenium (CdSe), cadmiumtellurium (CdTe), zinc sulfide (ZnS), zinc selenide (ZnSe), zinctelluride (ZnTe), tin telluride (SnTe), copper sulfide (Cu_(1-x)S (xvaries from 1 to 2)), copper selenide (Cu_(1-x)Se (x varies from 1 to2)), copper indium disulfide (CuInS₂), copper gallium disulfide(CuGaS₂), copper indium gallium disulfide, (Cu(In_(1-x)Ga_(x))S₂ (xvaries form 0 to 1)), copper indium diselenide (CuInSe₂), copper galliumdiselenide (CuGaSe₂), copper indium gallium diselenide(Cu(In_(1-x)Ga_(x))Se₂ (x varies form 0 to 1)), copper silver indiumgallium disulfide (Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))S (x varies form 0 to1, y varies form 0 to 1)), copper silver indium gallium diselenide(Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))Se₂ (x varies form 0 to 1, y varies form0 to 1)), indium sulfide (In₂S₃), indium selenide (In₂Se₃), aluminumnitride (AlN), indium nitride (InN), gallium nitride (GaN), bismuthsulfide (Bi₂S₃), antimony sulfide (Sb₂S₃), silver sulfide (Ag₂S),tungsten sulfide (WS₂), tungsten selenide (WSe₂), molybdenum sulfide(MoS₂), molybdenum selenide (MoSe₂), tin sulfide (SnS_(x) (x varies from1 to 2)), tin selenide (SnSe_(x) (x varies from 1 to 2)), and copper tinsulfide (Cu₄SnS₄).

The oxide material, for intrinsic semiconductor and oxide layers, mayinclude one or more of magnesium (Mg) oxide, aluminum (Al) oxide,silicon (Si) oxide, titanium (Ti) oxide, vanadium (V) oxido, chromium(Cr) oxide, manganese (Mn) oxide, iron (Fe) oxide, cobalt (Co) oxide,nickel (Ni) oxide, copper (Cu) oxide, zinc (Zn) oxide, gallium (Ga)oxide, germanium (Ge) oxide, selenium (Se) oxide, yttrium (Y) oxide,zirconium (Zr) oxide, niobium (Nb) oxide, molybdenum (Mo) oxide, indium(In) oxide, tin (Sn) oxide, antimony (Sb) oxide, tellurium (T) oxide,hafnium (Hf) oxide, tantalum (Ta) oxide, tungsten (W) oxide, mercury(Hg) oxide, lead (Pb) oxide, and bismuth (Bi) oxide.

For n-type semiconductor and oxide layers 21X1, for example, thesemiconductor material may be an n-type semiconductor comprising one ormore of silicon (Si), germanium (Ge), tin (Sn), beta iron silicide(β-FeSi₂), indium antimony (InSb), indium arsenic (InAs), indiumphosphate (InP), gallium phosphate (GaP), gallium arsenic (GaAs),gallium antimony (GaSb), aluminum antimony (AlSb), silicon carbide(SiC), tellurium (Te), zinc antimony (ZnSb), mercury telluride (HgTe),led sulfide (PbS), led selenide (PbSe), led telluride (PbTe), cadmiumsulfide (CdS), cadmium selenium (CdSe), cadmium tellurium (CdTe), zincsulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), tintelluride (SnTe), copper sulfide (Cu_(1-x)S (x varies from 1 to 2)),copper selenide (Cu_(1-x)Se (x varies from 1 to 2)), copper indiumdisulfide (CuInS₂), copper gallium disulfide (CuGaS₂), copper indiumgallium disulfide, (Cu(In_(1-x)Ga_(x))S₂ (x varies form 0 to 1)), copperindium diselenide (CuInSe₂), copper gallium diselenide (CuGaSe₂), copperindium gallium diselenide (Cu(In_(1-x)Ga_(x))Se₂ (x varies form 0 to1)), copper silver indium galliumdisulfide-(Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))S₂ (x varies form 0 to 1, yvaries form 0 to 1)), copper silver indium gallium diselenide(Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))Se₂ (x varies form 0 to 1, y varies form0 to 1)), indium sulfide (In₂S₃), indium selenide (In₂Se₃), aluminumnitride (AlN), indium nitride (InN), gallium nitride (GaN), bismuthsulfide (Bi₂S₃), antimony sulfide (Sb₂S₃), silver sulfide (Ag₂S),tungsten sulfide (WS₂), tungsten selenide (WSe₂), molybdenum sulfide(MoS₂), molybdenum selenide (MoSe₂), tin sulfide (SnS_(x) (x varies from1 to 2)), tin selenide (SnSe_(x) (x varies from 1 to 2)), copper tinsulfide (Cu₄SnS₄). Such semiconductors may be doped by adding animpurity of valence-five elements such as nitrogen (N), phosphorus (P),arsenic (As), or antimony (Sb)), in order to increase the number of free(in this case negative (electron)) charge carriers.

The oxide material, for n-type semiconductor and oxide layers, mayinclude one or more of magnesium (Mg) oxide, aluminum (Al) oxide,silicon (Si) oxide, titanium (Ti) oxide, vanadium (V) oxide, chromium(Cr) oxide, manganese (Mn) oxide, iron (Fe) oxide, cobalt (Co) oxide,nickel (Ni) oxide, copper (Cu) oxide, zinc (Zn) oxide, gallium (Ga)oxide, germanium (Ge) oxide, selenium (Se) oxide, yttrium (y) oxide,zirconium (Zr) oxide, niobium (Nb) oxide, molybdenum (Mo) oxide, indium(In) oxide, tin (Sn) oxide, antimony (Sb) oxide, tellurium (TI) oxide,hafnium (Hf) oxide, tantalum (Ta) oxide, tungsten (W) oxide, mercury(Hg) oxide, lead (Pb) oxide, and bismuth (Bi) oxide.

For p-type semiconductor and oxide layers 21X2, for example, thesemiconductor material may, be a p-type semiconductor comprising one ormore of silicon (Si), germanium (Ge), tin (Sn), beta iron silicide(β-FeSi₂), indium antimony (InSb), indium arsenic (InAs), indiumphosphate (InP), gallium phosphate (GaP), gallium arsenic (GaAs),gallium antimony (GaSb), aluminum antimony (AlSb), silicon carbide(SiC), tellurium (Te), zinc antimony (ZnSb), mercury telluride (HgTe),led sulfide (PbS), led selenide (PbSc), led telluride (PbTe), cadmiumsulfide (CdS), cadmium selenium (CdSe), cadmium tellurium (CdTe), zincsulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), tintelluride (SnTe), copper sulfide (Cu_(1-x)S (x varies from 1 to 2)),copper selenide (Cu_(1-x)Se (x varies from 1 to 2)), copper indiumdisulfide (CuInS₂), copper gallium disulfide (CuGaS₂), copper indiumgallium disulfide, (Cu(In_(1-x)Ga_(x))S₂ (x varies from 0 to 1)), copperindium diselenide (CuInSe₂) copper gallium diselenide (CuGaSe₂) copperindium gallium diselenide (Cu(In_(1-x)Ga_(x))Se2 (x varies from 0 to1)), copper silver indium gallium disulfide(Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))S2 (x varies from 0 to 1, y varies from0 to)), copper silver indium gallium diselenide(Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))Se₂ (x varies from 0 to 1, y varies from0 to 1)), indium sulfide (In₂S₃), indium selenide (In₂Se₃), aluminumnitride (AlN), indium nitride (InN), gallium nitride (GaN), bismuthsulfide (Bi₂S₃), antimony sulfide (Sb₂S₃), silver sulfide (Ag₂S),tungsten sulfide (WS₂), tungsten selenide (WSe₂), molybdenum sulfide(MoS₂), molybdenum selenide (MoSe₂), tin sulfide (SnS_(x) (x varies from1 to)), tin selenide (SnSe_(x) (x varies from 1 to)), copper tin sulfide(Cu₄SnS₄). Such semiconductors may be doped by adding an impurity ofvalence-three elements such as boron (B), aluminum (Al), gallium (Ga),or indium (In), in order to increase the number of free (in this casepositive (hole)) charge carriers.

The oxide material, for p-type semiconductor and oxide layers, mayinclude one or more of magnesium (Mg) oxide, aluminum (Al) oxide,silicon (Si) oxide, titanium (Ti) oxide, vanadium (V) oxide, chromium(Cr) oxide, manganese (Mn) oxide, iron (Fe) oxide, cobalt (Co) oxide,nickel (NI) oxide, copper (Cu) oxide, zinc (Zn) oxide, gallium (Ga)oxide, germanium (Ge) oxide, selenium (Se) oxide, yttrium (Y) oxide,zirconium (Zr) oxide, niobium (Nb) oxide, molybdenum (Mo) oxide, indium(In) oxide, tin (Sn) oxide, antimony (Sb) oxide, tellurium (Tl) oxide,hafnium (Hf) oxide, tantalum (Ta) oxide, tungsten (W) oxide, mercury(Hg) oxide, lead (Pb) oxide, and bismuth (Bi) oxide.

Metal and oxide layer 2200 includes a metal and an oxide. In aparticular implementation, the metal may be at least one metal materialselected from group consisting of Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr,Nb, Mo, Ru, Rh, Pd, Pt, Ag, Hf Ta, W, Re, Ir, Au. The oxide material maybe at least one oxide material selected from group consisting ofmagnesium (Mg) oxide, aluminum (Al) oxide, silicon (Si) oxide, titanium(Ti) oxide, vanadium (V) oxide, chromium (Cr) oxide, manganese (Mn)oxide, iron (Fe) oxide, cobalt (Co) oxide, nickel (Ni) oxide, copper(Cu) oxide, zinc (Zn) oxide, gallium (Ga) oxide, germanium (Ge) oxide,selenium (Se) oxide, yttrium (Y) oxide, zirconium (Zr) oxide, niobium(Nb) oxide, molybdenum (Mo) oxide, indium (In) oxide, tin (Sn) oxide,antimony (Sb) oxide, tellurium (Tl) oxide, hafnium (Hf) oxide, tantalum(Ta) oxide, tungsten (W) oxide, mercury (Hg) oxide, lead (Pb) oxide, andbismuth (Bi) oxide.

A.2. Electron Conducting Material Layer

Electron conducting material layer 1000 may be an oxide material, ann-type semiconductor material, or an organic electron conductingmaterial. Inorganic electron conducting materials, such as oxides andn-type semiconductors, may have a crystalline structure. The meltingtemperature of an inorganic electron conducting material layer (oxide orn-type semiconductor) and glass temperature of organic electronconducting layer should be above 80 C.

Electron conducting material layer 1000 may be an oxide materialincluding one or more of titanium (Ti) oxide (such as Ti0 ₂), aluminum(Al) oxide, cobalt (Co) oxide, silicon (Si) oxide, tin (Sn) oxide, zinc(Zn) oxide, molybdenum (Mo) oxide, tantalum (Ta) oxide, tungsten (W)oxide, indium (In) oxide, magnesium (Mg) oxide, bismuth (Bi) oxide,copper (Cu) oxide, vanadium (V) oxide, chromium (Cr) oxide. Electronconducting material layer 1000 may be an n-type semiconductor materialincluding one or more of silicon (Si), germanium (Ge), tin (Sn), betairon silicide (β-FeSi₂), indium antimony (InSb), indium arsenic (InAs),indium phosphate (InP), gallium phosphate (GaP), gallium arsenic (GaAs),gallium antimony (GaSb), aluminum antimony (AlSb), silicon carbide(SiC), tellurium (Te), zinc antimony (ZnSb), mercury telluride (HgTe),led sulfide (PbS), led selenide (PbSe), led telluride (PbTe), cadmiumsulfide (CdS), cadmium selenium (CdSe), cadmium tellurium (CdTe), zincsulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), tintelluride (SnTe), copper sulfide (Cu_(1-x)S (x varies from 1 to 2)),copper selenide (Cu_(1-x)Se (x varies from 1 to 2)), copper indiumdisulfide (CuInS₂), copper gallium disulfide (CuGaS₂), copper indiumgallium disulfide, (Cu(In_(1-x)Ga_(x))S₂ (x varies form 0 to 1)), copperindium diselenide (CuInSe₂), copper gallium diselenide (CuGaSe₂), copperindium gallium diselenide (Cu(In_(1-x)Ga_(x))Se₂ (x varies form 0 to1)), copper silver indium gallium disulfide(Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))S₂ (x varies form 0 to 1, y varies form0 to 1)), copper silver indium gallium diselenide(Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))Se₂ (x varies form 0 to 1, y varies form0 to 1)), indium sulfide (In₂S₃), indium selenide (In₂Se₃), aluminumnitride (AlN), indium nitride (InN), gallium nitride (GaN), bismuthsulfide (Bi₂S₃), antimony sulfide (Sb₂S₃), silver sulfide (Ag₂S),tungsten sulfide (WS₂), tungsten selenide (WSe₂), molybdenum sulfide(MoS₂), molybdenum selenide (MoSe₂), tin sulfide (SnS_(x) (x varies from1 to 2)), tin selenide (SnSe_(x) (x varies from 1 to 2)), copper tinsulfide (Cu₄SnS₄). Such semiconductors may be doped by adding animpurity of valence-five elements such as nitrogen (N), phosphorus (P),arsenic (As), or antimony (Sb), in order to increase the number of free(in this case negative (electron)) charge carriers.

Alternatively, electron conducting material layer 1000 may be an organicelectron conducting material such as perylene benzimidazole (PBI),perylene bis(piridylethylimide) (PPyEI), perylene.bis(phenethylimide)(PPEI) and [6,6]-phenyl-C₇₁-butyric acid methyl ester (PCBM).

A.3. Hole Conducting Material Layer

Hole conducting material layer 3000 may be a p-type semiconductor orother inorganic or organic hole conducting material. In a particularimplementation, the melting temperature of an inorganic hole conductingmaterial and the glass temperature of organic hole conducting materialshould be above 80 C.

In one implementation, hole conducting material layer 3000 may comprisea semiconductor material that may be doped by adding an impurity ofvalence-three elements such as boron (B) or aluminum (Al), in order toincrease the number of free (in this case positive (hole)) chargecarriers, including at least one of the following materials: silicon(Si), germanium (Ge), tin (Sn), beta iron silicide (β-FeSi₂), indiumantimony (InSb), indium arsenic (InAs), indium phosphate (InP), galliumphosphate (GaP), gallium arsenic (GaAs), gallium antimony (GaSb),aluminum antimony (AlSb), silicon carbide (SiC), tellurium (Te), zincantimony (ZnSb), mercury telluride (HgTe), led sulfide (PbS), ledselenide (PbSe), led telluride (PbTe), cadmium sulfide (CdS), cadmiumselenium (CdSe), cadmium tellurium (CdTe), zinc sulfide (ZnS), zincselenide (ZnSe), zinc telluride (ZnTe), tin telluride (SnTe), coppersulfide (Cu_(1-x)S (x varies from 1 to 2)), copper selenide (Cu_(1-x)Se(x varies from 1 to 2)), copper indium disulfide (CuInS₂), coppergallium disulfide (CuGaS₂), copper indium gallium disulfide,(Cu(In_(1-x)Ga_(x))S₂ (x varies form 0 to 1)), copper indium diselenide(CuInSe₂), copper gallium diselenide (CuGaSe₂), copper indium galliumdiselenide (Cu(In_(1-x)Ga_(x))Se₂ (x varies form 0 to 1)), copper silverindium gallium disulfide (Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))S₂ (x variesform 0 to 1, y varies form 0 to 1)), copper silver indium galliumdiselenide (Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))Se₂ (x varies form 0 to 1, yvaries form 0 to 1)), indium sulfide (In₂S₃), indium selenide (In₂Se₃),aluminum nitride (AlN), indium nitride (InN), gallium nitride (GaN),bismuth sulfide (Bi₂S₃), antimony sulfide (Sb₂S₃), silver sulfide(Ag₃S), tungsten sulfide (WS₂), tungsten selenide (WSe₂), molybdenumsulfide (MoS₂), molybdenum selenide (MoSe₂), tin sulfide (SnS_(x) (xvaries from 1 to 2)), tin selenide (SnSe₂ (x varies from 1 to 2)),copper tin sulfide (Cu₄SnS₄). Such semiconductors may be doped by addingan impurity of valence-three elements such as boron (B), aluminum (Al),gallium (Ga) or indium (In), in order to increase the number of free (inthis case positive (hole)) charge carriers. Other suitable p-typesemiconductor materials include copper thiocyanate (CuSCN), cuprousiodide (CuI), copper aluminum oxide (CuAlO₂) and organichole-conductors, such as spiro-OMeTAD(2,2′,7,7′-tretakis(N,N-di-p-methoxyphenyl-amine)-9-9′-spirobifluorene)(partial oxidation of spiro-OMeTAD by N(PhBr)₃SbCl₆ can be used tocontrol the dopant level), MEH-PPV[poly[2-methoxy-[5-(2′-ethyl)hexyl]oxy-p-phenylenevinylene]], PEDOT:PSS[poly(3,4-ethylenedioxythiophene)poly(styrenesulfonate)](to increase itsconductivity PEDOT:PSS can be mixed with glycerin, N-methylpyrrolidone,and isopropanol.

B. Fabrication of Photovoltaic Cell Layers

The semiconductor and oxide layers can be fabricated using a sputterdeposition process (such as magnetron sputtering) in order to produce alayer structure that comprises semiconductor grains surrounded by anoxide matrix. Sputtering conditions and other process settings result indispersal of oxide at grain boundaries of the semiconductor, and controlthe diameter of semiconductor grains and the ratio between the volumefraction of semiconductor and oxide materials. In a particularimplementation, a semiconductor and oxide layer including semiconductorgrains isolated in a matrix of oxide can be prepared by sputtering ametal interlayer (such as an Ru interlayer) and then cosputtering asemiconductor with an oxide material with low adatom mobility. The oxidematerial moves into the semiconductor grain boundaries and isolates thesemiconductor grains. To reduce decomposition of oxide duringsputtering, an oxide material with large diatomic bond strength betweenmetal and oxygen can be used.

As discussed above, the semiconductor grains 98 have a generallycylindrical or columnar shape where the dimension of the cylinderdepends on the semiconductor grain diameter and the thickness of thesemiconductor and oxide layer. The ratio between the volume fraction ofoxide and semiconductor material can be controlled by varying thecomposition of sputtering target (source). Additionally, the diameter ofabsorber semiconductor grains can be controlled by sputtering aninterlayer prior to sputtering the semiconductor and oxide layer.Semiconductor grains in the semiconductor and oxide layer grow on top ofthe interlayer grains while oxide is dispersed around the semiconductorgrains. Thus, in most instances, the diameter of interlayer grains cancontrol or strongly influence the diameter of semiconductor grains inthe semiconductor and oxide layer deposited on the interlayer.Sometimes, if the interlayer grains are too large (over 15 nm), it isalso possible that two or more semiconductor grains grow on a singleinterlayer grain. The interface area between semiconductor grains 98 andoxide (both the oxide matrix and oxide in an adjacent layer) depends onthe semiconductor grain diameter and the thickness of the semiconductorand oxide layer. However, the interface area can be over 100 timeslarger than that for a flat junction between an oxide layer and asemiconductor layer or films. As illustrated above, the semiconductorand oxide layer can be located between an oxide material (or othern-type semiconductor) and a p-type semiconductor (or other holeconducting material) that can also be sputtered with magnetronsputtering. This layer structure is used in solar cells where thesemiconductor grains absorb the solar radiation. This process alsoallows fabrication of multilayer structures with semiconductor grainssurrounded with oxide materials, where an oxide material preferentiallygrows on top of an oxide material and a semiconductor materialpreferentially grows on top of a semiconductor material. In multilayerstructures the composition of oxide and semiconductor in each layer canbe varied separately to increase the efficiency of photon conversion.

In an example sputtering process, argon (Ar) ions strike a sourcegenerating atoms that are deposited on a substrate as shown in FIG. 6.Positive argon ions may be accelerated toward the source by applyingnegative potential on the source. The distance from the target to thesubstrate is D and Ar pressure in the sputter chamber is p. Mobility ofatoms deposited on the substrate is affected by the kinetic energy ofthe deposited atoms as well as the kinetic energy of Ar neutrals thatstrike the substrate surface. Ar ions that strike the target sourcereceive an electron and bounce off the source as Ar neutrals. If theseAr neutrals strike the substrate surface they increase the mobility ofthe deposited atoms. High pressure in the sputtering chamber, p, willalso increase the probability of collision between Ar neutrals and therest of the Ar atoms in the chamber reducing E_(k) of the Ar neutralsand reducing the effect of Ar neutrals on mobility of deposited atoms.In addition, a low negative voltage bias may be applied to the substrateto influence or further control surface mobility.

Similarly, the kinetic energy, E_(k), and angle, α, (see FIG. 7) atwhich deposited atoms land on a substrate surface depend on Ar pressurein the sputtering chamber. If the pressure is high, the probability ofcollisions between deposited atoms and Ar atoms is larger resulting in areduction of E_(k) (atoms) and an increase of α of the deposited atoms(see FIG. 7). In other words, these collisions alter the direction orangle at which atoms are deposited on the substrate surface. As FIG. 7illustrates, α is an angle between the direction that is normal to thefilm plane and the direction of deposited atom. Without collisions withAr atoms, the majority of atoms will be deposited at low α angles (i.e.,closer to perpendicular to the substrate surface). Collisions increasethe average deposition angle α resulting in reduced deposition rate inthe valleys in comparison to the tops of the substrate surface.

As an example, a ruthenium (Ru) interlayer can be sputtered at highpressure 6 Pa (45 mTorr) of Ar on a seed layer. Sputtering at higherpressure reduces the mean free path of sputtered Ru atoms (and Arneutrals reflected from a Ru target) due to collisions with Ar atoms ontheir path from target to substrate. The collisions reduce the kineticenergy of deposited Ru atoms reducing surface diffusion of Ru atoms, andrandomize the angle at which Ru atoms are deposited onto the substrateaway from the direction that is normal to film surface. This causesroughness to increase with increasing film thickness because the “tops”of neighboring column structures block the adatoms incidentline-of-sight path to the “valleys”. Thus, the sputtering rate in the“valleys” is lower than that on the “tops” of the rough area due to theshadowing effect. Continued growth under controlled sputteringconditions (such as low temperature and high pressure) therefore resultsin increasingly voided (physically separated) columnar structures.

Applying a similar sputtering process to a composite target of (orotherwise co-sputtering) a semiconductor and an oxide results in asimilar structure. That is, the semiconductor atoms deposited on thesubstrate surface form columnar structures during the sputteringprocess, while the oxide material is dispersed by the semiconductorgrain boundaries forming a matrix that surrounds or isolates thesemiconductor grains. In addition, a metal material may be added to thesemiconductor and oxide layer to promote growth of the desiredcomposition and microstructure of the semiconductor and oxide layer. Themetal material may be at least one of the following materials: Al, Ti,V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Pt, Ag, Hf, Ta, W,Re, Ir, and Au. The metal material may be embodied in a separate targetand co-sputtered with semiconductor and oxide target(s) or be mixed intothe same target.

While the semiconductor and oxide layer can be formed directly on anoxide or other layer, it can also be grown or sputter deposited on aninterlayer, such as an Ru interlayer (as formed above), which induces orpromotes vertical columnar or grain axis growth in the semiconductor andoxide layer. That is, the interlayer can control the crystallographicgrowth orientation, grain diameter of semiconductor and most importantlysurface roughness required for segregating oxide in grain boundaries.For example, cosputtering of semiconductor and oxide, under highpressure, causes semiconductor grains to grow on top of the Ru grainswith oxide segregating to semiconductor grain boundaries.

Still further, after deposition of one or more semiconductor and oxidelayers, the structure may be annealed in the presence of inert orreactive gasses to obtain desired composition, compound and crystalstructures and/or to reduce defects. Annealing temperatures may vary upto 1000 degrees C.; however, annealing temperatures in the range of 150to 600 degrees C. are preferred. After a given annealing step, thestructure is preferably cooled if the next layer to be sputtered is alsosemiconductor and oxide layer.

In a particular implementation, a semiconductor and oxide layer can beformed using a magnetron sputtering in the presence of a gas, under oneor more of the following sputtering conditions: 1) a total atmosphericpressure during sputtering of at least 0.8 Pa (6 mTorr); 2) an appliedbias on a substrate during the sputtering of less than 400 V, and 3) atemperature of a substrate during the sputtering below 200 degrees C.Total atmospheric pressure in the chamber, p_(tot), required to achievethe segregation of oxide to grain boundaries in the semiconductor andoxide layer depends on the distance from source to the substrate, D, andthe deposition rate, DR, (the number of atoms that land on a substrateper second and can be also defined as a thickness of the deposited layerper second). As D increases, oxide segregation at semiconductor grainboundaries can be achieved with lower p_(tot) pressure. If D increasesthe probability of collisions between deposited atoms and Ar atomsincreases. On the other hand, as DR increases, p_(tot) pressure has tobe higher to lower the surface mobility of deposited atoms required forthe oxide segregation. For example, if D=2 cm, and DR is larger than 1nm/s, p_(tot) pressure should be larger than 1.8 Pa (10 mTorr). If D=2cm, and DR is larger than 5 nm/s, p_(tot) pressure should be larger than2 Pa (15 mTorr). If D=5 cm, and DR is larger than 1 nm/s, p_(tot)pressure should be larger than 1 Pa (8 mTorr). If D=10 cm, and DR islarger than 1 nm/s, p_(tot) pressure should be larger than 0.8 Pa (6mTorr). If D=10 cm, and DR is larger than 5 nm/s, p_(tot) pressureshould be larger than 1 Pa (8 mTorr).

In some cases a negative bias can be applied to the substrate. The biasincreases mobility of deposited atoms on the substrate surface. Thesemiconductor and oxide layer is sputtered with the bias that is lessthan 400 Volts (V). In many instances, the bias can be below 200 V. Inaddition, the semiconductor and oxide layer can be sputtered in thepresence of at least one of the gasses argon (Ar), krypton (Kr) andxenon (Xe). The semiconductor and oxide layer can be sputtered in areactive environment that, in addition to one or more of Ar, Kr and Xe,can also contain oxygen (Os), nitrogen (Ni), hydrogen (H), hydrogensulfide (H₂S), and hydrogen selenide (H₂Se). The semiconductor and oxidelayer can be sputtered from a single target including both semiconductorand oxide materials, or co-sputtered at the same time from two or moredifferent targets. The semiconductor and oxide layer can be alsoannealed in CdCl₂ vapors.

As mentioned above, in order to obtain surface roughness that canimprove oxide segregation, an interlayer can be sputtered prior tosputtering the semiconductor and oxide layer. The presence of theinterlayer can improve crystallographic growth of the semiconductor andoxide layer and narrow the diameter distribution of semiconductorgrains. FIGS. 1 d and 1 g illustrate different possible interlayerstructures that can be formed. Interlayer 5000 may include 1) one ormore metallic layers, 2) one or more semiconductor layers, or 3) one ormore oxide layers. Alternatively, as FIG. 11 shows, the interlayer 5001may comprise one or more layers of a metal and an oxide material, wherethe oxide is dispersed at grain boundaries of the metal.

Suitable metals for the interlayer 5000 or 5001 include Al, Ti, V, Cr,Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, andAu. Suitable semiconductors for the interlayer 5000 or 5001 include Si,Ge, Sn, β-FeSi₂, InSb, InAs, InP, GaP, GaAs, GaSb, AlSb, SiC, Te, ZnSb,HgTe, PbS, PbSe, PbTe, CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, SnTe, Cu_(1-x)S(x=1 to 2), Cu_(1-x)Se (x=1 to 2), CuInS₂, CuGaS₂, Cu(In_(1-x)Ga_(x))S₂(x=0 to 1), CuInSe₂, CuGaSe₂, Cu(In_(1-x)Ga_(x))Se₂ (x=0 to 1)),(Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))S₂ (x=0 to 1, y=0 to 1),(Cu_(1-x)Ag_(x))(In_(1-y)Ga_(y))Se₂ (x=0 to 1, y=0 to 1), In₂S₃, In₂Se₃,AlN, InN, GaN, Bi₂S₃, Sb₂S₃, Ag₂S, WS₂, WSe₂, MoS₂, MoSe₂, SnS_(x) (x=1to 2), SnSe_(x) (x=1 to 2), Cu₄SnS₄. Suitable oxide materials for theinterlayer 5000 or 5001 include magnesium (Mg) oxide, aluminum (Al)oxide, silicon (Si) oxide, titanium (Ti) oxide, vanadium (V) oxide,chromium (Cr) oxide, manganese (Mn) oxide, iron (Fe) oxide, cobalt (Co)oxide, nickel (Ni) oxide, copper (Cu) oxide, zinc (Zn) oxide, gallium(Ga) oxide, germanium (Ge) oxide, selenium (Se) oxide, yttrium (Y)oxide, zirconium (Zr) oxide, niobium (Nb) oxide, molybdenum (Mo) oxide,indium (In) oxide, tin (Sn) oxide, antimony (Sb) oxide, tellurium (Tl)oxide, hafnium (Hf) oxide, tantalum (Ta) oxide, tungsten (W) oxide,mercury (Hg) oxide, lead (Pb) oxide, and bismuth (Bi) oxide. Theinterlayer can sputtered with a magnetron sputtering technique, wherethe sputtering conditions comprise one or more of 1) a total atmosphericpressure of at least 0.8 Pa (6 mTorr), 2) an applied bias to thesubstrate of less than 400 V, and 3) a substrate temperature of below200 C. The interlayer can be also first sputtered at a total atmosphericpressure below 0.8 Pa (6 mTorr), and then sputtered at a totalatmospheric pressure above 1.6 Pa (12 mTorr) to achieve columnar growthof interlayer grains and to promote growth of semiconductor grains ontop of the interlayer grains with oxide segregating to semiconductorgrain boundaries. Sputtering can be performed in at least one of thegasses, Ar, Kr and Xe. Sputtering can be also performed in a reactiveenvironment that also contains oxygen (O₂), nitrogen (N₂), hydrogen (H),hydrogen sulfide (H₂S), and hydrogen selenide (H₂Se). The interlayer canbe subsequently annealed in an environment that contains argon (Ar),krypton (Kr), xenon (Xe), oxygen (Os), nitrogen (Na), hydrogen (H),hydrogen sulfide (H₂S), hydrogen selenide (H₂Se) and/or CdCl₂ vapors.

In order to further improve growth of the interlayer and therefore thesemiconductor and oxide layer 21Xy, a seed layer 6000 can be sputteredon the substrate before sputtering the interlayer 5000. A method ofmanufacturing the semiconductor and oxide layer can comprise sputterdepositing the seed layer 6000 with a magnetron sputtering technique ata total atmospheric pressure less than 0.8 Pa (6 mTorr) and a substratetemperature below 200 C, and then sputter depositing the interlayer 5000under conditions including a total atmospheric pressure of at least 1.3Pa (10 mTorr), an applied substrate bias less than 400 V, and asubstrate temperature less than 150 C. The method may further comprisesputter depositing a semiconductor and oxide layer 21Xy under conditionsincluding a total atmospheric pressure of at least 1.3 Pa (10 mTorr), anapplied substrate bias less than 200 V, and a substrate temperaturebelow 150 C. The foregoing is only intended to be illustrative. Otherprocess conditions can also be used.

Sputtering of seed layer 6000 can be performed in at least one of thegasses, Ar, Kr and Xe. Sputtering can be also performed in the reactiveenvironment that also contains oxygen (O₂), nitrogen (N₂), hydrogen (H),hydrogen sulfide (H₂S), and hydrogen selenide (H₂Se) with a totalsputtering pressure lower than 1.8 Pa (10 mTorr). During the sputteringof the seed layer 6000 a bias voltage may be applied to the substrate toincrease mobility of deposited atoms while growing the seed layer toyield a smooth layer surface that promotes desired growth and structureof the interlayer 5000.

A benefit of the high pressure sputtering processes described herein isthe formation of semiconductor grains separated by an oxide matrix. Thismicrostructure is desired in solar cells where semiconductor grainsinject electrons in the conductive band of an oxide and/or n-typesemiconductor material and holes in the valence band of hole conductingmaterial. Relaxation rates of hot carriers are very fast in bulksemiconductors. However, the rate can be slowed if semiconductor graindiameter is reduced below about 10 to 20 nm. This allows the extractionof hot carriers before they can relax to the band edge, or generation oftwo or more electron-hole pairs from a single photon increasing theefficiency of the photon conversion in nanometer-sized semiconductorabsorbers. The high pressure sputtering process can be used to producesemiconductor grains with the average diameter below 10 nm. The averagesemiconductor grain diameter can be controlled by varying one or moreof 1) sputtering pressure of the seed layer, interlayer and/or thesemiconductor and oxide layer, 2) the thickness of the seed layer andthe interlayer, and 3) the ratio between the semiconductor and oxidevolume fraction in the semiconductor and oxide layer. Furthermore, theshape of the semiconductor grains can be controlled using a highpressure sputtering process. By changing the semiconductor and oxidelayer thickness, for example, the shape of the semiconductor grains canbe varied from that of a thin to that of thick cylindrical like shape.

As FIGS. 2 a and 2 b (for example) illustrate, the high pressuresputtering method can also be used to create a composite semiconductorand oxide layer having multiple sub-layers (“SOL sub-layer”). One ormore characteristics of each semiconductor and oxide layer may be variedto achieve desired results, such as varying semiconductor grain diameterand height to vary the resulting band gap of the semiconductor grains.For example, each SOL sub-layer may contain the same or differentsemiconductor materials. Each SOL sub-layer may contain the same ordifferent oxide materials. In addition the ratio between thesemiconductor and oxide volume fraction can be varied across the layers.

The described flexibility of the process is quite advantageous for solarcells because it allows varying the band gap, E_(g), of semiconductorgrains in each SOL sub-layer. For example, assume that semiconductor andoxide absorption layers 2110, 2120, 21N0 in a solar cell are designed asshown in FIG. 2 a and that solar illumination enters from the top of thelayer structure. To increase efficiency of the solar cell, energy orband gap, E_(g), of semiconductor grains can be varied from a largervalue in the top sub-layer 21N0 to a smaller value in the bottomsub-layer 2110. The band gap can be varied between about 0.5 to 3.5 eVto capture or take advantage of a broader spectrum of light energy. Theband gap, E_(g), of semiconductor grains can be varied by changing thediameter and height of the semiconductor grains in the SOL sub-layersand/or by changing the composition of the semiconductor grains.

FIGS. 1 a to 1 g illustrate possible solar cell structures that may beconstructed using the photoactive conversion layers including one ormore semiconductor and oxide layer, as well as seed layer 6000 andinterlayer 5000, disposed between two electrodes. A variety ofconfigurations are possible. For example, seed layer 6000 may be anelectrical contact or electrode layer. Electric contacts (such astransparent conductive layers, metal grids and layers), non-reflectivecoatings, and/or protective layers can also be added to the layeredstructure of the solar cell as described above. Additional example solarcell structures are described below in Section C.

C. Alternative Cell Structures and Configurations

FIG. 2 a shows a solar cell structure according to which is deposited inoverlying sequence, a seed layer 6000, an interlayer 5000, an n-typesemiconductor and oxide layer 2101, an intrinsic semiconductor and oxidelayer 2110, a p-type semiconductor or other hole conducting materiallayer 3000. As mentioned above, multiple intrinsic semiconductor andoxide layers 21X0 can be deposited. As mentioned above, layers 2101,2110 can be deposited with a magnetron sputtering technique at a totalatmospheric pressure of at least 1.2 Pa (10 mTorr). A seed layer 6000can be also first sputtered at a total atmospheric pressure below 0.8 Pa(6 mTorr), and then sputtered at a total atmospheric pressure above 1.6Pa (12 mTorr) to form an interlayer 5000 to promote desired growth ofsemiconductor grains of the n-type semiconductor and oxide layer 2101.Hole conducting material layer 3000 can sputtered at a total atmosphericpressure below 1.2 Pa (10 mTorr).

FIG. 2 b illustrates an alternative embodiment including p-typesemiconductor and oxide layer 2102 sputtered deposited on the interlayer5000, and an electron conducting material layer 1000 deposited on theintrinsic semiconductor and oxide layer 2110.

FIG. 3 a illustrates a cell structure according to which is deposited,in overlying sequence, a seed layer 6000, an interlayer 5000, an n-typesemiconductor and oxide layer 2101, an intrinsic semiconductor and oxidelayer 2110, one or more p-type semiconductor and oxide layers 21 n 2,and a p-type semiconductor or other hole conducting material layer 3000.As mentioned above, multiple intrinsic semiconductor and oxide layers21X0 can be deposited. In another implementation, the intrinsicsemiconductor and oxide layer can be omitted. Additionally, multiplep-type semiconductor and oxide layers 21X2 can be deposited between thelast intrinsic semiconductor and oxide layer 21N0 and the holeconducting material layer 8000. Similarly, multiple n-type semiconductorand oxide layers 21X1 can be deposited between the interlayer 5000 andthe first intrinsic semiconductor and oxide layers 2110. In someimplementations, a thin layer of oxide can be deposited between each, orselect ones, of these multiple semiconductor and oxide layers 21Xy tosegregate the semiconductor grains. The diameter and height ofsemiconductor grains and the composition of semiconductor grains inlayers 21Xy can be varied to vary band gap of semiconductor material andincrease efficiency of the cell structures. In a particularimplementation, the size of the semiconductor grains in the firstsemiconductor and oxide layer 21X0 is the largest (relative to all othersemiconductor and oxide layers), with semiconductor grain sizedecreasing with each successive layer. In addition, as FIG. 3 cillustrates, a metal and oxide layer 2200 can also be deposited on theinterlayer 5000 to underlie the n-type semiconductor and oxide layer2101.

FIG. 3 b illustrates a cell structure according to which is deposited,in overlying sequence, a seed layer 6000, an interlayer 5000, a p-typesemiconductor and oxide layer 2102, an intrinsic semiconductor and oxidelayer 2110, and one or more n-type semiconductor and oxide layers 21 n1, and electron conducting material layer 1000. As mentioned above,multiple intrinsic semiconductor and oxide layers 21X0 can be deposited.Additionally, multiple n-type semiconductor and oxide layers 21X1 can bedeposited between the last intrinsic semiconductor and oxide layer 21N0and the electron conducting material layer 1000. Similarly, multiplep-type semiconductor and oxide layers 21X2 can be deposited between theinterlayer 5000 and the first intrinsic semiconductor and oxide layers2110. In some implementations, a thin layer of oxide can be depositedbetween each, or select ones, of these multiple semiconductor and oxidelayers 21Xy to segregate the semiconductor grains.

Still further, as FIGS. 3 d and e show, in any of the foregoingconfigurations, an intervening layer (3500, 3510, . . . , 35(n+1)0),such as a thin layer of oxide, may be deposited between each of thesemiconductor and oxide layers 21Xy to isolate the semiconductor grains.The thickness of layers 3500, 3510, . . . , 35(n+1)0 can be up to 200nm. Preferably, in one implementation, the thickness of layers 3500,3510, . . . , 35(n+1)0 is up to 20 nm.

The photoactive conversion layer 80 may also include one or more metaland oxide layers. FIG. 4 a illustrates a cell structure according towhich is deposited, in overlying sequence, a seed layer 6000, aninterlayer 5000, an n-type semiconductor and oxide layer 2101, a metaland oxide layer 2200, a p-type semiconductor and oxide layer 2122, and ap-type semiconductor or other hole conducting material layer 3000.Additionally, multiple n-type semiconductor and oxide layers 21X1 can bedeposited between interlayer 5000 and the metal and oxide layer 2200.Similarly, multiple p-type semiconductor and oxide layers 21X2 can bedeposited between the metal and oxide layers 2200 the hole conductingmaterial layer 3000. In addition, one or more intrinsic semiconductorand oxide layers 21X0 can be deposited. FIG. 4 b illustrates a cellstructure according to which is deposited, in overlying sequence, a seedlayer 6000, an interlayer 5000, a p-type semiconductor and oxide layer2102, a metal and oxide layer 2200, an n-type semiconductor and oxidelayer 2121, and electron conducting material layer 1000. Additionally,multiple n-type semiconductor and oxide layers 21X1 can be depositedbetween the metal and oxide layer 2200 and the electron conductingmaterial layer 1000. Similarly, multiple p-type semiconductor and oxidelayers 21X2 can be deposited between the interlayer 5000 and the metaland oxide layers 2200. As mentioned above, one or more intrinsicsemiconductor and oxide layers 21X0 can also be deposited.

As FIGS. 5 a to 5 e illustrate, some of the layers discussed above canbe omitted from photoactive conversion layer 80. Electron and holeconducting layers 1000 or 3000, as well as seed layer 6000 andinterlayer 5000, may be omitted. For example, as FIG. 5 a shows,photoactive conversion layer may comprise one or more p-typesemiconductor and oxide layers 2102, one or more intrinsic semiconductorand oxide layers 2110, and one or more n-type semiconductor and oxidelayers 2101. FIG. 5 b illustrates the addition of seed layer 6000 andinterlayer 5000. FIG. 5 c illustrates the addition of a metal and oxidelayer 2200. Lastly, FIGS. 5 d and 5 e show the addition of thinintervening layers 3500, 3510, . . . , 35(n+1)0 deposited between thesemiconductor and oxide layers 21Xy.

In other implementations, tandem solar cells can be constructedutilizing one or more semiconductor and oxide layers. FIG. 8 aillustrates a cell structure according to which is deposited, inoverlying sequence, a seed layer 6000, an interlayer 5000, and one ormore composite layer structures including an n-type semiconductor andoxide layer 2101, a p-type semiconductor and oxide layer 2112, and aninterconnecting layer 3600. The cell structure further includes ann-type semiconductor and oxide layer 21 n 1, a p-type semiconductor andoxide layer 21(n+1)2, and a hole conducting material layer 3000. A cellstructure illustrated in FIG. 8 b also includes intrinsic semiconductorand oxide layers 21X0 deposited between n-type and p-type semiconductorand oxide layers of the composite layer structures.

FIG. 9 a illustrates a cell structure according to which is deposited,in overlying sequence, a seed layer 6000, an interlayer 5000, and one ormore composite layer structures including an n-type semiconductor andoxide layer 2101, a p-type semiconductor and oxide layer 2112, and aninterconnecting layer 3600. The illustrated cell structure also includesan n-type semiconductor and oxide layer 21 n 1, and a p-typesemiconductor and oxide layer 21(n+1)2. A cell structure illustrated inFIG. 9 b also includes intrinsic semiconductor and oxide layers 21X0deposited between n-type and p-type semiconductor and oxide layers ofthe composite layer structures.

An interconnecting layer 3600 may include one or more oxide (ofparticular interest are conductive oxides such as indium-tin-oxide anddoped zinc oxide) or semiconductor layers. The interconnecting layer3600 can be up to 200 nm in thickness. In one implementation, theinterconnecting layer is about 20 nm or less in thickness. The role ofthe interconnecting layer 3600 is to connect sub-cells (p-n junctions).Preferably, the inter-cell ohmic contacts should cause very low loss ofelectrical power between cells. Therefore, the interconnecting layer3600 should have minimal electrical resistance. For this reasoninterconnecting layer can be metal, conductive oxide layer, and a tunneljunction (or tunnel diodes). The metal interconnects can provide lowelectrical resistance, but they are difficult to fabricate and theystrongly absorb light that can cause substantial loss in the deviceefficiency. Therefore, conductive oxide layers, tunnel junctions (ortunnel diodes) are preferred. The material used for interconnectinglayer 3600 should have low resistivity, low optical energy losses, andoften crystallographic compatibility through lattice-matching betweentop and bottom cell.

In the previous description, numerous specific details are set forth,such as specific materials, structures, processes, etc., in order toprovide a better understanding of the present invention. However, thepresent invention can be practiced without resorting to the detailsspecifically set forth. In other instances, well-known processingmaterials and techniques have not been described in detail in order notto unnecessarily obscure the present invention. Only the preferredembodiments of the present invention and but a few examples of itsversatility are shown and described in the present disclosure. It is tobe understood that the present invention is capable of use in variousother combinations and is susceptible of changes and/or modificationswithin the scope of the inventive concept as expressed herein.

What is claimed is:
 1. A photovoltaic cell, comprising a first layercomprising an electron conducting material; a second layer comprising ahole conducting material; and wherein at least one of the first andsecond layers comprises a plurality of absorber semiconductor grains andan oxide material dispersed at boundaries of the absorber semiconductorgrains.
 2. The photovoltaic cell of claim 1 further comprising a one ormore additional semiconductor and oxide layers, disposed between thefirst layer and the second layer, each comprising semiconductor materialand an oxide material, wherein the oxide material is dispersed at grainboundaries of the semiconductor material.
 3. The photovoltaic cell ofclaim 2 wherein at least one of the semiconductor and oxide layers isseparated from an adjacent semiconductor and oxide layer with anintervening oxide layer.
 4. A photovoltaic cell, comprising aninterlayer; a semiconductor and oxide layer comprising an oxide and ann-type semiconductor, wherein the oxide is dispersed at grain boundariesof the n-type semiconductor; and a hole conducting material layer. 5.The photovoltaic cell of claim 4 wherein the interlayer comprises ametal.
 6. The photovoltaic cell of claim 4 wherein the hole conductingmaterial layer comprises a p-type semiconductor.
 7. The photovoltaiccell of claim 4 further comprising a seed layer, wherein the interlayeris deposited on the seed layer.
 8. The photovoltaic cell of claim 4further comprising a transparent conductive layer formed on the holeconducting material layer.
 9. The photovoltaic cell of claim 8 furthercomprising a transparent protective layer formed over the transparentconductive layer.
 10. The photovoltaic cell of claim 4 furthercomprising a metal and oxide layer, disposed between the interlayer andthe semiconductor and oxide layer, comprising an oxide and a metal,wherein the oxide is dispersed at grain boundaries of the metal.
 11. Thephotovoltaic cell of claim 4 further comprising a second semiconductorand oxide layer, disposed between the semiconductor and oxide layer andthe hole conducting material layer, comprising an intrinsicsemiconductor and an oxide, wherein the oxide is dispersed at grainboundaries of the intrinsic semiconductor.
 12. The photovoltaic cell ofclaim 11 wherein at least one of the semiconductor and oxide layers isseparated from an adjacent semiconductor and oxide layer with anintervening oxide layer.
 13. The photovoltaic cell of claim 11 furthercomprising a third semiconductor and oxide layer, disposed between thesecond semiconductor and oxide layer and the hole conducting materiallayer, comprising an oxide and a p-type semiconductor, wherein the oxideis dispersed at grain boundaries of the p-type semiconductor.
 14. Thephotovoltaic cell of claim 4 further comprising a semiconductor andoxide layer, disposed between the semiconductor and oxide layer and thehole conducting material layer, comprising an oxide and a p-typesemiconductor, wherein the oxide is dispersed at grain boundaries of thep-type semiconductor.
 15. The photovoltaic cell of claim 4 furthercomprising a metal and oxide layer, disposed between the semiconductorand oxide layer and the hole conducting material layer, comprising anoxide and a metal, wherein the oxide is dispersed at grain boundaries ofthe metal.
 16. The photovoltaic cell of claim 4 further comprising asecond semiconductor and oxide layer, disposed between the semiconductorand oxide layer and the hole conducting material layer, comprising anoxide and an p-type semiconductor, wherein the oxide is dispersed atgrain boundaries of the p-type semiconductor, and a metal and oxidelayer, disposed between the semiconductor and oxide layer and the secondsemiconductor and oxide layer, comprising an oxide and a metal, whereinthe oxide is dispersed at grain boundaries of the metal.
 17. Aphotovoltaic cell, comprising a interlayer; a semiconductor and oxidelayer comprising an oxide and an p-type semiconductor, wherein the oxideis dispersed at grain boundaries of the p-type semiconductor, and anelectron conducting material layer.
 18. The photovoltaic cell of claim17 wherein the electron conducting material layer comprises an n-typesemiconductor.
 19. The photovoltaic cell of claim 17 further comprisinga seed layer, wherein the interlayer is deposited on the seed layer. 20.The photovoltaic cell of claim 17 further comprising a transparentconductive layer formed on the electron conducting material layer.